UNC- Charlotte ECGR 2181 - Fall 2009 - Logic Systems Design I
Recitation - All Sections: 8:00 - 10:45 F, Woodward 125
Lecture: Section 001: 9:30 - 10:45, M/W, Woodward 140
Lecture: Section 002: 2:00 - 3:15, T/Th, Woodward 140
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Computer Assignments

This page updated

December 3, 2009


Computer Assignment 5,  Due 3:00 pm, Wednesday, December 9 (both sections).

Computer Assignment 4,  Due 3:00 pm, Wednesday, December 2 (both sections).

Computer Assignment 3,  Due 3:00 pm, Wednesday, November 11 (both sections).

Computer Assignment 2,  Due 3:00 pm, Wednesday, November 4 (both sections).
  • Assignment (pdf file). - note there was a change Friday afternoon to correct a typo.  You all received an email.
  • Solution is available on the Moodle site for the course. 

Computer Assignment 1,  Due 3:00 pm, Wednesday, October 28 (both sections).

Computer Assignment hints and tool bugs
  1. ModelSim License Error when trying to run Simulation on the Test Bench
    Solution: Close Xilinx ISE and re-open ISE directly from the Start Menu -> Mosaic XP -> Engineering -> Electrical -> Xilinx Webpack -> Xilinx ISE 7.1i
    Reason: Mosaic's Application Launcher is getting called and needs to be called for the license server's environment variable to be set. If you just double click on the ISE Project File to launch ISE, the launcher is not called and thus the env. vars aren't set. GRRRR

  2. Simulation of Test Bench results in a VHW file in Read Mode Error
    Root of Problem: The entire path of the project must NOT contain any spaces. So if they saved the file as:
       U:\pc\win_data\Desktop\Computer Assignment 1
    this will cause all kinds of problems because Xilinx is using TCL scripts that were written LONG ago that don't allow for spaces in paths! (Again, GRRR) Solution: If the student already created the project directory, simply create a new directory WITHOUT spaces and run ISE to create a new project. You can import the project files form the old project (and check the copy to new project) so that the files will actually be copied into the new directory). Once this is done this problem should go away.

  3. So after doing computer assignment 8, I went to run my test bench and was confronted by this error again
    # ** Error: (vcom-7) Failed to open design unit file "tb.vhw" in read mode.
    # No such file or directory. (errno = ENOENT)
    # ** Error: i:/apps/winnt/modsim61e/Modeltech_6.1e/win32/vcom failed.

    Remembering what was said in class I checked my paths for spaces, but could find none. Upon further investigation I discovered something else. Reading the transcript of xillinx when it compiled my testbench I found:

    Compiling vhdl file "//afs/jkrause3/pc/win_data/desktop/comp3b/aluv2.vhd" in Library work.

    Compare this to the same output on my computer assignment 2 which does simulate:

    Compiling vhdl file "u:/pc/win_data/desktop/comp2/aluvhdl.vhd" in Library work.

    Keep in mind both these files are saved on my desktop.

    One is using a path referencing the u: drive, and the other is using the relative path of my accounts network harddrive. I'm pretty sure this is caused by the nature of mosaic; because I started AND finished assignment 2 without logging out of mosaic while I started and stopped assignment 3 twice, using different remote workstations each time. I believe modelsim can't correctly read network harddrive paths (which wouldn't surprise me considering it can't read spaces either) and that is what is leading to this read mode error.

    After messing with it for an extended period of time I found a successful workaround. The trick is, when opening your project in xillinx you can't use any of the left-panel shortcut buttons. Instead, you must manually navigate to your project folder from the U: drive. Like this:
    My computer -> U: -> pc -> win_data -> desktop -> (whatever the file name).

    Now when the test-bench is run it will work without the readmode error. Saving the file after running the simulation seems to "fix" the issue as well, allowing the project to be opened the easy way and have the simulation still continue to work.

    I tested this multiple times, even with my original non-working file from assignment 0 and it has worked each time.
    Interestingly, after using the workaround, the simulation compiling transcript still shows a network path, but modelsim works regardless.

    Thought I'd share this, since I'm sure that other people have suffered from the same problem.