library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --------------------------------------------------------------------------- -- Entity Definition for sequence_compare_vhdl -- Inputs to this component are: sequence and guess -- Ouput from this component is: num_correct --------------------------------------------------------------------------- entity sequence_compare_vhdl is Port ( sequence : in std_logic_vector(7 downto 0); guess : in std_logic_vector(7 downto 0); num_correct : out std_logic_vector(7 downto 0)); end sequence_compare_vhdl; --------------------------------------------------------------------------- -- ARCHITECTURE for the sequence_compare_vhdl entity --------------------------------------------------------------------------- architecture Behavioral of sequence_compare_vhdl is ------------------------------------------------------------------- -- All Signal and Component Declarations are placed between the -- "architecture Behavorial ..." line above and the "begin" -- found a few lines below. These signals are like the lines -- used to connect components together in a schematic. ------------------------------------------------------------------- -- Signal to store Equality Comparison of sequence and guess inputs signal eq_compare : std_logic_vector(7 downto 0); -- Integer to store the total number of Ones in eq_compare signal signal sum_ones : integer; --------------------------------------------------------------------------- -- BEGIN for the architecture of sequence_compare_vhdl -- All VHDL code which uses the Entity's input ports, signals and -- components created above to generate the Entity's output ports go here --------------------------------------------------------------------------- begin ------------------------------------------------------------------- -- Step 1: Compare the Sequence to the Guess (note that both -- sequence and guess are input ports in the entity -- definition). Which GATE is used to "compare equality" -- between two signals? -- Replace the word "GATE" with the appropriate gate. Then -- add the remaining boolean equations for bits 6 through 0 ------------------------------------------------------------------- eq_compare(7) <= sequence(7) GATE guess(7); ------------------------------------------------------------------- -- Step 2: eq_compare is an 8-bit register which denotes whether -- or not the sequence and guess for each bit position -- are the same. 1 indicates equality and 0 indicates -- inequality. Inorder to know how many bits were correct -- you must add all 8 bits up. So if Player 1 set the -- sequence to 11000110 and Player 2 guessed 11001100 then: -- 11000110 (sequence) -- 11001100 (guess) -- 11110101 (eq_compare result from Step 1) -- 1+1+1+1+0+1+0+1 = 6 (to be used in Step 3) -- Complete the Sumation by adding the remaining bits -- 5 through 0. "conv_integer" function converts -- the std_logic data type to an integer. The + operator -- only works on integers. ------------------------------------------------------------------- sum_ones <= conv_integer(eq_compare(7)) + conv_integer(eq_compare(6)) + ------------------------------------------------------------------- -- Step 3: num_correct_output process which will be sensitive to -- the Step 2 variable "sum_ones" and will work very -- similiar to a decoder except instead of outputing a -- single 1, it will output x number of 1s. So if -- sum_ones = 6 then the num_correct output should be -- num_correct <= "00111111" -- Remember num_correct is the only output port for the -- sequence_compare_vhdl component. It will be connected -- to a register in the TOP vhdl file that will be connected -- to the 8 LEDs. When the user guesses, the number -- of bits in the correct position will be shown on the LEDs -- Add the correct signal the process's Sensitivity List -- and then complete the remaining cases (3 through 6) ------------------------------------------------------------------- num_correct_output : process (SIGNAL) is begin case (SIGNAL) is when 0 => num_correct <= "00000000"; when 1 => num_correct <= "00000001"; when 2 => num_correct <= "00000011"; -- TODO: Complete the remaining cases 3-6 when 7 => num_correct <= "01111111"; when others => num_correct <= "11111111"; end case; end process num_correct_output; end Behavioral;