library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --------------------------------------------------------------------------- -- Entity Definition for sequence_top_vhdl -- Inputs to this component are: clk, rst, set, guess, slide_switches -- Ouput from this component is: leds_out --------------------------------------------------------------------------- entity sequence_top_vhdl is Port ( clk : in std_logic; rst : in std_logic; set : in std_logic; guess : in std_logic; slide_switches : in std_logic_vector(7 downto 0); leds_out : out std_logic_vector(7 downto 0)); end sequence_top_vhdl; --------------------------------------------------------------------------- -- ARCHITECTURE for the sequence_top_vhdl entity --------------------------------------------------------------------------- architecture Behavioral of sequence_top_vhdl is ------------------------------------------------------------------- -- All Signal and Component Declarations are placed between the -- "architecture Behavorial ..." line above and the "begin" -- found a few lines below. These signals are like the lines -- used to connect components together in a schematic. ------------------------------------------------------------------- -- Finite State Machine (FSM) Signals -- This FSM consists of 5 states which are declared below type SEQUENCE_FSM_TYPE is (idle, wait_for_sequence, wait_for_guess, compare_sequences, done); -- Two signals (fsm_cs = current state) and (fsm_ns = next state) -- are used in place of (s2,s1,s0 and n2,n1,n0) the state bits -- and allow you to easily transition from current state to -- the next state every clock cycle. signal fsm_cs : SEQUENCE_FSM_TYPE := idle; signal fsm_ns : SEQUENCE_FSM_TYPE := idle; -- Temporary Signals used to connect Components -- Identify where they are used or should be used -- and also be able to answer what their purpose is for. signal sequence_reg : std_logic_vector(7 downto 0); signal guess_reg : std_logic_vector(7 downto 0); signal num_correct_out : std_logic_vector(7 downto 0); signal sequence_set : std_logic; signal guess_set : std_logic; signal led_set : std_logic; -- Component Declaration of sequence_compare_vhdl COMPONENT sequence_compare_vhdl PORT(sequence : IN std_logic_vector(7 downto 0); guess : IN std_logic_vector(7 downto 0); num_correct : OUT std_logic_vector(7 downto 0)); END COMPONENT; -- Component Declaration of register_8_bit_sch COMPONENT register_8_bit_sch PORT(set : IN STD_LOGIC; rst : IN STD_LOGIC; flp : IN STD_LOGIC; clk : IN STD_LOGIC; d : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END COMPONENT; --------------------------------------------------------------------------- -- BEGIN for the architecture of sequence_top_vhdl -- All VHDL code which uses the Entity's input ports, signals and -- components created above to generate the Entity's output ports go here --------------------------------------------------------------------------- begin ------------------------------------------------------------------- -- Step 1: The Finite State Machine's "fsm_state_proc" process -- is used to progress the current state to the next state -- every clock cycle. In the event of a reset the FSM -- should return to the idle state. -- Complete the two lines of code setting the fsm_cs. ------------------------------------------------------------------- fsm_state_proc : process (clk) is begin -- If the Clock is on a Rising Edge if ((clk'event) and (clk='1')) then -- If there is a Reset, return to the Idle State if (rst = '1') then fsm_cs <= ; else -- Otherwise set the "new" current state to the next state fsm_cs <= ; end if; end if; end process fsm_state_proc; ------------------------------------------------------------------- -- Step 2: The Finite State Machine's "fsm_comb_proc" process -- is the Combinational Circuit Logic that would typically -- come from the State Table's KMAP reduction. VHDL -- offers a significant advantage in not only avoiding -- KMAPs, but also to avoid being limited to -- the gate representation of the circuit. -- Below the Finite State Machine's Case Statement is -- provided with each state. However, some outputs -- and transition If statements are not provided or are -- incomplete. Complete the missing VHDL. ------------------------------------------------------------------- -- Finite State Machine Combinational Process fsm_comb_proc : process (fsm_cs, rst, guess, set, slide_switches, sequence_reg, guess_reg) is begin -- Finite State Machine's Case Statement case (fsm_cs) is --------------------------------------------------- -- Idle State 0: Initial State to clear ('0') -- the contents of the three register set bits. -- Output: sequence_set, guess_set and led_set -- Next State: wait_for_sequence --------------------------------------------------- when idle => sequence_set <= ; guess_set <= ; led_set <= ; fsm_ns <= ; --------------------------------------------------- -- Wait For Sequence State 1: Wait for Player 1 to -- press the "set" push button. Allow the -- sequence_set signal to be set when it is pressed. -- Do not allow guess_set or led_set to be asserted. -- Transition to wait_for_guess state when set = '1' -- Otherwise wait in this state (wait_for sequence) --------------------------------------------------- when wait_for_sequence => sequence_set <= ; guess_set <= ; led_set <= ; if then fsm_ns <= ; else fsm_ns <= wait_for_sequence; end if; --------------------------------------------------- -- Wait For Guess State 2: Wait for Player 2 to -- press the "guess" push button. Allow the -- guess_set signal to be set when it is pressed. Do -- not allow sequence_set or led_set to be asserted. -- Transition to the compare_sequences state when -- guess = '1' Otherwise wait in this state. --------------------------------------------------- when wait_for_guess => sequence_set <= ; guess_set <= ; led_set <= ; if then fsm_ns <= ; else fsm_ns <= ; end if; --------------------------------------------------- -- Compare Sequences State 3: Allow the component -- sequence_compare_vhdl to compare and produce -- the valid "num_correct" output which will -- be stored in the led register. Allow the -- led_set signal to be set immediately ('1') and -- do not allow sequence_set or guess_set to be -- asserted. If sequence = guess then transition -- to the done state. Otherwise return to the -- wait_for_guess state. --------------------------------------------------- when compare_sequences => sequence_set <= ; guess_set <= ; led_set <= ; if then fsm_ns <= ; else fsm_ns <= ; end if; --------------------------------------------------- -- Done State 4: Stay in the done state until the -- user presses the reset button. This is because -- Player 2 correctly guessed the sequence and -- the game is over. --------------------------------------------------- when done => sequence_set <= '0'; guess_set <= '0'; led_set <= '0'; fsm_ns <= done; end case; end process fsm_comb_proc; ------------------------------------------------------------------- -- sequence_compare_vhdl component instance -- Correctly connect the sequence and guess inputs and the -- num_correct output. Look at the signals declared above to -- determine which signals should be connected to which ports. ------------------------------------------------------------------- seq_comp_i : sequence_compare_vhdl PORT MAP( sequence => , guess => , num_correct => ); ------------------------------------------------------------------- -- Sequence Register - 8 Bit register. Correctly connect the -- input and output ports. flp is forced to '0' because in this -- game there is no flipping of the LEDs. -- Consider what signal declared above should be used to "set" -- the register to the slide_switches content. ------------------------------------------------------------------- seq_req_i : register_8_bit_sch PORT MAP( clk => , rst => , set => , flp => '0', d => , q => ); ------------------------------------------------------------------- -- Guess Register - 8 Bit register. Correctly connect the -- input and output ports. flp is forced to '0' because in this -- game there is no flipping of the LEDs. -- Consider what signal declared above should be used to "set" -- the register to the slide_switches content. ------------------------------------------------------------------- guess_req_i : register_8_bit_sch PORT MAP( clk => , rst => , set => , flp => '0', d => , q => ); ------------------------------------------------------------------- -- LED Register - 8 Bit register. Correctly connect the -- input and output ports. flp is forced to '0' because in this -- game there is no flipping of the LEDs. -- Consider what signal declared above should be used to "set" -- the register to the num_correct content. ------------------------------------------------------------------- led_reg_i : register_8_bit_sch PORT MAP( clk => , rst => , set => , flp => '0', d => , q => ); end Behavioral;