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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/17/2015 06:01:25 PM
-- Design Name: 
-- Module Name: task1_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity task2_tb is
--  Port ( );
end task2_tb;

architecture Behavioral of task2_tb is

	--declaring the component
	component task2
	    Port ( a : in STD_LOGIC;
	       b : in STD_LOGIC;
	       c : in STD_LOGIC;
	       d : in STD_LOGIC;
	       y : out STD_LOGIC);
	end component;

	--declaring the signals needed
	--these y,a,b signals are different from the
	--internal ones of the component
	signal counter:		unsigned(3 downto 0):="0000";
	signal y,a,b, c ,d:	std_logic;

begin
	-- component assignment
	uut: task2 port map(
		a => a,
		b => b,
		c => c,
		d => d,
		y => y
	);

	--assignint a and b to the counter bits so that
	--all possible inputs are tested
	a <= counter(0);
	b <= counter(1);
	c <= counter(2);
	d <= counter(3);
		
	--increments the counter
	tb: process
	begin
		wait for 20ns;
		counter <= counter + 1;
	end process tb;

end Behavioral;