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-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/08/2015 08:31:10 PM
-- Design Name: 
-- Module Name: top_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_tb is
--  Port ( );
end top_tb;

architecture Behavioral of top_tb is

	component top is
	Port (
		sw       : in  STD_LOGIC_VECTOR (7 downto 0);
		seg      : out std_logic_vector(6 downto 0);
		dp       : out std_logic;
		an       : out std_logic_vector(3 downto 0);
		led      : out STD_LOGIC_VECTOR (7 downto 0);
		btnL     : in  std_logic;
		btnR     : in  std_logic;
		clk      : in  std_logic
	);
	end component;

	constant clk_per : time := 10ns;

	signal sw        : std_logic_vector(7 downto 0);
	signal seg       : std_logic_vector(6 downto 0);
	signal dp        : std_logic;
	signal an        : std_logic_vector(3 downto 0);
	signal led       : STD_LOGIC_VECTOR (7 downto 0);
	signal btnL      : std_logic;
	signal btnR      : std_logic;
	signal clk       : std_logic := '0';
	
begin

	uut: top port map (
		sw     => sw,
		seg    => seg,
		dp     => dp,
		an     => an,
		led    => led,
		btnL   => btnL,
		btnR   => btnR,
		clk    => clk
	);		
	
	btnL_proc: process
	begin
		btnL <= '0';
		wait for clk_per*11;
		
		btnL <= '1';
		wait for clk_per*1;
	end process btnL_proc;

	btnR_proc: process
	begin
		btnR <= '0';
		sw <= x"01";
		wait for clk_per*119;
		
		btnR <= '1';
		sw <= x"ff";
		wait for clk_per;
		
		btnR <= '0';
		wait;
	end process btnR_proc;
	
	clk_proc: process
	begin
		wait for clk_per/2;
		clk <= not(clk);
	end process clk_proc;

end Behavioral;