UNC- Charlotte ECGR2181-001- Spring 2006

Logic Systems Design I

Lecture, 3:30 - 4:50 PM, T/TH, Woodward 140
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Lab 6,  Perform and turn in Tuesday, May 2.

 

Homework 12,  Due Tuesday, May 2, BEGINNING OF CLASS!!!!

Lab 5,  Perform and turn in Thursday, April 27.

 

Homework 11,  Due Tuesday, April 25, BEGINNING OF CLASS!!!!

Homework 10,  Due Tuesday, April 18, BEGINNING OF CLASS!!!!
  •  0) "How long did this homework take you?"
    1) Book problem 6.20e
    2) Modify the Verilog program in Table 6-26 (p. 409) to also display hex characters a, b, c, d, e, f.  You will need to modify existing characters.

Homework 9,  Due Tuesday, April 11, BEGINNING OF CLASS!!!!

Lab 4,  Perform and turn in Tuesday, March 28.

 

Homework 8,  Due Tuesday, March 28, BEGINNING OF CLASS!!!!

Lab 3,  Perform and turn in Thursday, March 16.

Homework 7,  Due Thursday, March 16, BEGINNING OF CLASS!!!!

Lab 2,  Perform and turn in Thursday, March 2.

Homework 6,  Due Thursday, March 2, BEGINNING OF CLASS!!!!

Lab 1,  Perform and turn in Tuesday, February 21.

Homework 5,  Due Tuesday, February 21, BEGINNING OF CLASS!!!!

Homework 4,  Due Thursday, February 9, BEGINNING OF CLASS!!!!

Homework 3,  Due Thursday, February 2, BEGINNING OF CLASS!!!!

Homework 2,  Due Tuesday, January 24, BEGINNING OF CLASS!!!!

Homework 1,  Due Tuesday, January 17, BEGINNING OF CLASS!!!!