Use this lab report template for the report which is due. Don't forget to print your VHDL code files and attach them to the report.
Homework 8, Due Tuesday, April 4, BEGINNING OF CLASS!!!!
Problems 5.19d, 5.20. Show all work! Also, question 0 is: "How long did this homework take you?" Do them before the test - they may appear on the test!
Homework 7, Due Thursday, March 24, BEGINNING OF CLASS!!!!
Due: Draw a flow chart which shows the processes of creating a design all the way through programming and testing the FPGA board. Show blocks representing large activities you need to do (not individual keystrokes!). Limit your flowchart to 20 blocks.
Computer Lab Assignment 1, Due Tuesday, March 22, BEGINNING OF CLASS!!!!